Co-Design Imperative: Early Prevention of Integration Problems

HW/SW co-design assumes concurrent development of software and hardware which means that different parts of the system a
re developed in parallel to be integrated in the product. Even when much care has been taken to define good HW/SW interfaces and
to analyse/evaluate specification and architectural decomposition, it is likely that a number of unforeseen problems remain in the
system conception and design due to:

  • Learning process: new customer use-cases, design and technologies means that not all details about system behavior and performance can be known up front, and they can only be learned as the development progresses
  • Evolution: changes in requirements and technological and market evolutions may result in some of the initial assumptions becoming invalid
  • Ever-increasing complexity of products and technologies means that not all interactions can be foreseen
  • Local decisions: design decisions made by individual engineers or teams in their local context without realizing their impact on the rest of the system introduce new problems

These problems need to be uncovered and addressed as soon as possible, to minimise cost and delays due to rework after integration

Therefore methods for risk analysis, model-based testing, simulation techniques - and more generally of early prevention of integrations problems are a key imperative of HW/SW co-design

Following table lists all TWINS solutions and experience reports that address this co-design imperative.

ESSENTIAL ACTIVITIES CO-DESIGN IMPERATIVE: Early Prevention of Integration Problems
Requirements Management Disambiguating Requirements
Solutions

Supervisory control for hybrid systems

HoR - House Of Requirements

Experience Reports

Sioux DSL Experience Reports

HoR - House Of Requirements

Architecture Architectural Consistency
Solutions

Scaleo EasyTLMtranslator

Murphy - Product Assumptions

Experience Reports
HW/SW simulation & emulation Resource Management
Solutions

SystemC TLM/TLM-T Simulation Platform

Rhapsody panels and abstract interfaces

SIL, Software In the Loop, Simulation

SIL, Software In the Loop, Simulation

Prototype printer visualization

Visualization of a printer simulation

Interactive visualization

Real-Time Step Motor Emulation

Experience Reports

SystemC TLM/TLM-T Simulation Platform

SIL, Software In the Loop, Simulation

Verification and validation Model Based Checking and Testing
Solutions

SysEmulator

Automatic test generation for SystemC models

Supervisory control for hybrid systems

SIL, Software In the Loop, Simulation

SIL, Software In the Loop, Simulation

Prototype printer visualization

Visualization of a printer simulation

Interactive visualization

Real-Time Step Motor Emulation

Automatic verification and analysis of test results

Breadth-Bounded Model Checking

Analysis of Boolean Equation Systems through Structure Graphs

Co-simulation Environment for an Advanced Current Measurement Application

TestWORKFLOW for Test Management & Execution

Automatic unit test generation for C++ programs

Experience Reports

SysEmulator

Verum ASD

SIL, Software In the Loop, Simulation

Co-simulation Environment for an Advanced Current Measurement Application

TestWORKFLOW for Test Management & Execution

Automatic unit test generation for C++ programs

Management Risk Analysis
Solutions

Murphy - Risk Management of Failure

Barco NPI Process

Exploiting System Re-configurability to Minimize HW/SW Co-Design Risk

Experience Reports

Exploiting System Re-configurability to Minimize HW/SW Co-Design Risk